1. Field of the Invention
The present invention relates to spread-spectrum communication systems and, more particularly, to the recovery of the digital clock timing by the receiver in spread-spectrum digital communication systems.
2. Statement of the Problem
In digital communication systems in general, the recovery of timing is difficult and usually significantly contributes to the overhead of the operating system. In spread spectrum systems, the maximal sequence length is 2.sup.n -1 chips; for n=7, the maximal length is 127 chips. In nonsynchronous digital systems for example, the provision of start and stop bits can be utilized to provide the necessary bit and byte timing information. The use of such start/stop bits, however, adds to the overhead and reduces the bandwidth of the transmitted digital data. In other approaches, the clock is encoded with the data stream or the clock is related to the carrier frequency that is transmitted.
Word synch is conventionally generated by sending a specific pattern of data bits called "word synch" that signals the start of the data field. The longer the pattern of data bits, the more accurate the detection of the word clock and the less likely it is to find a false synch location. The provision of a long word synch contributes significantly to the overhead of a time slot.
One conventional approach to clock extraction is to use a synchronous method to extract the clock from the carrier signal. Synchronous methods require generally complex circuits including carrier multipliers and phase lock loops in order to function. Such hardware can be expensive and relatively slow in operation. For example, phase lock loops require time to lock on to the correct phase. In TDMA or TDD systems this means adding a longer section to the time slot which means more overhead and less bandwidth.
Therefore, conventional methods of bit and word clock extraction suffer from a high degree of complexity. The accuracy of extraction degrades when interference or low signal levels exist. In conventional spread-spectrum digital communication systems, the digital clock timing for the despread digital data is generated from the despread signal. Hence, a receiver first despreads the received signal and then recovers digital clock timing from the despread signal. The circuitry for despreading and clock recovery are separate and costly.
A need exists, especially in portable telephony environments, to obtain digital clock timing for the despread digital data from the receiver's despreader in order to reduce the cost and complexity of the receiver. Hence, a need exists to generate digital timing inexpensively with low overhead in the time slot.
3. Solution to the Problem
The present invention provides a solution to the above problem by providing a spread-spectrum digital communication system in which the recovery of the bit clock, the nibble clock, and/or the byte clock are derived from the pseudo random sequence generator at the receiver. Expensive circuitry for recovery of digital timing from the despread digital data is not required. This is accomplished by adding a chip to the conventional 2.sup.n -1 pseudo random sequence used to spread and despread the digital data. For example, where n=7, 127+1=128 chips are used for the sequence. The pseudo random signal generator is designed so that when the number of chips per bit used to spread the digital information at the transmitter is divided into the number of chips in the sequence length an integer value results. The time slots of digital information contained in each transmitted frame are spread wherein a fixed number of chips per bit is provided and wherein the chips per bit are aligned with each bit of digital information. Furthermore, the time for the sequence length of M bits when divided into the time for a time slot also results in an integer value. At the receiver, the clock which drives the pseudo random signal generator is also utilized to provide the digital timing for the despread digital information. Hence, the present invention provides a solution to the above problem by aligning the chips of the spreading sequence with the digital bits of the spread data and by meeting the above integer criteria.